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Micrel, Inc.
An external reference clock, when used instead of a
crystal, should be applied to pin 24 (XTALOUT) with pin
23 (XTALIN) not connected. To maintain proper DC
biasing within the chip, use AC-coupling between the
external reference and the XTALOUT-pin.
MICRF507
The modulator clock is used if VCO modulation method
is selected. Set the modulator clock frequency to either
8x or 16x the bit rate. See “VCO Modulation and the
Modulator” subsection for more information.
BITSYNC_CLK (Receiver Bit Synchronization Clock)
BitRate_clkS[2:0]
Corresponding Clock
The frequency of the
bit synchronization clock
BitSync_clkS[2:0]
Frequency
f XCO
f BITSYNC_CL K =
f BITSYNC_CLK , is a function of the crystal oscillator
frequency f XCO and the values of the register fields
Refclk_K and BitSync_clkS:
Refclk_K × 2 (7 - BitSync_cl kS )
The bit synchronizer uses a clock that needs to be
programmed to 16 times the actual bit rate. As an
example, a bit rate of 20kbps needs a bit synchronizer
clock with frequency of 320kHz. Refer to Figure 9 and
“Data Interface and Bit Synchronization” section for more
Mod_clkS[2:0]
000
001
010
011
100
101
110
111
(f XCO is crystal frequency)
f XCO /(128xRefClk_K)
f XCO /(64xRefClk_K)
f XCO /(32xRefClk_K)
f XCO /(16xRefClk_K)
f XCO /(8xRefClk_K)
f XCO /(4xRefClk_K)
f XCO /(2xRefClk_K) (*)
f XCO /RefClk_K (*)
=
f BITRATE_CL K
f MOD_CLK =
details.
BITRATE_CLK (Transmitter Bit Rate Clock)
The frequency f BITRATE_CLK of BITRATE_CLK is a function
of the crystal oscillator frequency f XCO and the values of
the register fields Refclk_K and BitRate_clkS:
f XCO
Refclk_K × 2 (7 - BitRate_cl kS)
In transmit mode, when Sync_en = 1, BITRATE_CLK
appears on the DATACLK pin. Its frequency is equal to
the bit rate. Example; a bit rate of 20 kbit/sec requires an
f BITRATE_CLK of 20kHz. Refer to Figure 9 and the “Data
Interface and Bit Synchronization” subsection for more
details.
MODULATOR_CLK (VCO Modulator Clock)
The frequency f MOD_CLK of MODULATOR_CLK is a
function of the crystal oscillator frequency f XCO and the
values of the register fields Refclk_K and Mod_clkS:
f XCO
Refclk_K × 2 (7 - Mod_clkS )
(*) Can not be used as BitRate_clk.
Table 5. Generation of Bitrate_clk, BitSync_clk
and Mod_clk
Data Interface and Bit Synchronization
Transmitted and received data bits are coupled to the
MICRF507 serially through the Data Interface. This Data
Interface consists of the DATAIXO and DATACLK pins.
This is a separate interface from the Control Interface
(CS, IO, and SCLK), for which see Control (3-wire)
Interface.
Figure 9 shows the data interface circuitry aboard the
MICRF507. DATAIXO is an input during transmission,
whereas during reception a driver is enabled and it
becomes an output. DATACLK is always an output.
A rule that applies when using VCO modulation is: after
commanding the MICRF507 to enter transmit mode, the
microcontroller shall tri-state the driver connected to
DATAIXO to leave that pin floating until the
microcontroller begins sending data. See “Mode
Transitions” section for more details.
The data interface can be programmed for synchronous
and non-synchronous operation according to the setting
of the Sync_en bit; see Table 7.
October 2, 2013
17
Revision 2.2
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